Cryptoraptor : high throughput reconfigurable cryptographic processor for symmetric key encryption and cryptographic hash functions

textIn cryptographic processor design, the selection of functional primitives and connection structures between these primitives are extremely crucial to maximize throughput and flexibility. Hence, detailed analysis on the specifications and requirements of existing crypto-systems plays a crucial role in cryptographic processor design. This thesis provides the most comprehensive literature review that we are aware of on the widest range of existing cryptographic algorithms, their specifications, requirements, and hardware structures. In the light of this analysis, it also describes a high performance, low power, and highly flexible cryptographic processor, Cryptoraptor, that is designed to support both today's and tomorrow's encryption standards. To the best of our knowledge, the proposed cryptographic processor supports the widest range of cryptographic algorithms compared to other solutions in the literature and is the only crypto-specific processor targeting the future standards as well. Unlike previous work, we aim for maximum throughput for all known encryption standards, and to support future standards as well. Our 1GHz design achieves a peak throughput of 128Gbps for AES-128 which is competitive with ASIC designs and has 25X and 160X higher throughput per area than CPU and GPU solutions, respectively.Electrical and Computer Engineerin

From plasma to beefarm: Design experience of an FPGA-based multicore prototype

In this paper, we take a MIPS-based open-source uniprocessor soft core, Plasma, and extend it to obtain the Beefarm infrastructure for FPGA-based multiprocessor emulation, a popular research topic of the last few years both in the FPGA and the computer architecture communities. We discuss various design tradeoffs and we demonstrate superior scalability through experimental results compared to traditional software instruction set simulators. Based on our experience of designing and building a complete FPGA-based multiprocessor emulation system that supports run-time and compiler infrastructure and on the actual executions of our experiments running Software Transactional Memory (STM) benchmarks, we comment on the pros, cons and future trends of using hardware-based emulation for research.Peer ReviewedPostprint (author's final draft

High performance hardware architectures for one bit transform based single and multiple reference frame motion estimation

Motion Estimation (ME) is the most computationally intensive part of video compression and video enhancement systems. One bit transform (1BT) based ME algorithms have low computational complexity. Therefore, in this paper, we propose high performance systolic hardware architectures for 1BT based fixed block size (FBS) single reference frame (SRF) ME, variable block size (VBS) SRF ME, and multiple reference frame (MRF) ME. The proposed FBS-SRF ME hardware performs full search ME for 4 Macroblocks in parallel and it is faster than the 1BT based ME hardware reported in the literature. In addition, it uses less on-chip memory than the previous 1BT based ME hardware by using a novel data reuse scheme and memory organization. The proposed VBS-SRF ME hardware is also faster and uses less on-chip memory than previous 1BT based VBS-SRF ME hardware. The proposed MRF ME hardware is the first 1BT based MRF ME hardware in the literature. In order to trade-off ME performance and computational complexity, the proposed MRF ME hardware is designed as reconfigurable in order to statically configure the number and selection of reference frames based on the application requirements. The proposed hardware architectures are implemented in Verilog HDL. They are capable of processing 83 1920x1080 full High Definition frames per second. Therefore, they can be used in consumer electronics products that require real-time video processing or compression.(1

A reconfigurable hardware for one bit transform based multiple reference frame motion estimation

Motion Estimation (ME) is the most computationally intensive part of video compression and video enhancement systems. One bit transform (1BT) based ME algorithms have low computational complexity. Therefore, in this paper, we propose a high performance reconfigurable hardware architecture of 1BT based multiple reference frame (MRF) ME. The proposed ME hardware architecture performs full search ME for 4 Macroblocks and 4 reference frames in parallel. The proposed hardware is faster than the 1BT based ME hardware reported in the literature even though it is capable of searching in 4 reference frames. MRF ME increases the ME performance at the expense of increased computational complexity. The reconfigurability of the proposed ME hardware is used to statically configure the number and selection of reference frames based on the application requirements in order to trade-off ME performance and computational complexity. The proposed hardware architecture is implemented in Verilog HDL. The MRF ME hardware consumes %65 of the slices in a Xilinx XC2VP30-7 FPGA. It can work at 191 MHz in the same FPGA and is capable of processing 83 1920 × 1080 full High Definition frames per second

A low energy adaptive hardware for H.264 multiple reference frame motion estimation

Multiple reference frame motion estimation (MRF ME) increases the video coding efficiency at the expense of increased computational complexity and energy consumption. Therefore, in this paper, a low complexity H.264 MRF ME algorithm and a low energy adaptive hardware for its real-time implementation are proposed. The proposed MRF ME algorithm reduces the computational complexity of MRF ME by using a dynamically determined number of reference frames for each Macroblock (MB) and early termination. The proposed H.264 MRF ME hardware is implemented in Verilog HDL. The proposed H.264 MRF ME hardware has 29-72% less energy consumption than an H.264 MRF ME hardware using 5 reference frames for all MBs with a negligible PSNR loss. Therefore, it can be used in consumer electronics products that require real-time video processing or compression with low power consumption

Pregnancy and Kidney Transplantation: A Single-Center Experience

Objective: The possibility of pregnancy increases with kidney transplantation in patients with chronic kidney disease. However, graft dysfunction, risk of fetal growth retardation, and fetal anomaly should be monitored closely. In this study, renal and obstetric outcomes were analyzed in pregnant kidney recipients who were followed in our center. Methods: We analyzed 140 reproductive-aged patients who underwent renal transplantation between January 2009 and May 2015, and clinical and laboratory data were evaluated retrospectively. Results: Twenty-four patients became pregnant (17.1%). In pregnant group, median age was significantly lower than nonpregnant group (P =.014). The median age of pregnant group at the time of transplantation was also significantly lower than non-pregnant patients (P 35 age group (odds ratio = 48.39; 95% CI: 1.26-1860.72; P =.037). Rejection episodes were observed in 1 of pregnant women and 11 of non-pregnant women (P >.05). Conclusion: Pregnancy is possible in kidney transplant recipients of reproductive age. Calcineurin inhibitors and azathioprine seem to be safe. Maternal age, low-serum creatinine, and urinary proteinuria affect pregnancy. The close monitoring of renal function and fetal parameters is very important

A novel power reduction technique for block matching motion estimation hardware

Motion Estimation (ME) is the most computationally intensive part of video compression and video enhancement systems. Therefore, in this paper, we propose comparison prediction (CP) technique for reducing the power consumption of block matching (BM) ME hardware. CP technique reduces the power consumption of absolute difference operations performed by BM ME hardware. CP technique can easily be used in all BM ME hardware. In this paper, we applied it to a 256 processing element fixed block size ME hardware implementing full search algorithm. It reduced the average dynamic power consumption of this ME hardware by 2.2% with no Peak Signal-to-Noise Ratio (PSNR) loss and by 9.3% with 0.04% PSNR loss on a XC2VP30-7 FPGA

From plasma to beefarm: Design experience of an FPGA-based multicore prototype

In this paper, we take a MIPS-based open-source uniprocessor soft core, Plasma, and extend it to obtain the Beefarm infrastructure for FPGA-based multiprocessor emulation, a popular research topic of the last few years both in the FPGA and the computer architecture communities. We discuss various design tradeoffs and we demonstrate superior scalability through experimental results compared to traditional software instruction set simulators. Based on our experience of designing and building a complete FPGA-based multiprocessor emulation system that supports run-time and compiler infrastructure and on the actual executions of our experiments running Software Transactional Memory (STM) benchmarks, we comment on the pros, cons and future trends of using hardware-based emulation for research.Peer Reviewe